The breakthrough afforded by the Chatter AMPIC DRAM architecture of data switching, and switching and routing amongst network I/O source and destination resources, as described in the above-referenced patent, has enabled orders of magnitude faster transfer of blocks of data internal to the chip, and the accommodation of significantly higher numbers of resources, with the reduction of current serious bandwidth limitations. This architecture has also given rise to higher performance, lower system latency, less data packet buffer memory requirements, better QOS features, and true multicast operation, which current and traditional networking architectures have been unable to achieve.
As the number of I/O resources in such systems explodes, and with it the concomitant demand for even further increases in bandwidth, however, the data packet information packet itself (herein termed "PIP") becomes the limiting factor in this type of system, It is to the addressing of these issues through a novel control path architecture--itself adopting and using the AMPIC DATA technology also in the control path--that the present invention is concerned. The invention, indeed, creates a control path architecture for such AMPIC DATA switching and routing systems that scales with the data path, while still maintaining QOS functionality and providing improved multicast performance.